SyncReadMem generated verilog vs. Rocketchip emitted verilog

I am using SyncReadMem() for sram behavioral simulation. With the (generated Verilog)[] by verilator, I hope to replace it with a commercial sram compiler compiled verilog such that I can do synthesis for the whole design including sram.

However, I noticed that the verilog emitted by SyncReadMem() is not with uniform IOs just like the (sram emitted in rocketchip)[]. I wonder how do we generate some sram verilog just like the rocketchip one, using chisel mem API like SyncReadMem()?

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