SyncReadMem generated verilog vs. Rocketchip emitted verilog

I am using SyncReadMem() for sram behavioral simulation. With the (generated Verilog)[https://gist.github.com/HaFred/22a416bb0291b7dd9e2187a50cb470c0] by verilator, I hope to replace it with a commercial sram compiler compiled verilog such that I can do synthesis for the whole design including sram.

However, I noticed that the verilog emitted by SyncReadMem() is not with uniform IOs just like the (sram emitted in rocketchip)[https://github.com/chipsalliance/rocket-chip/blob/master/scripts/vlsi_mem_gen]. I wonder how do we generate some sram verilog just like the rocketchip one, using chisel mem API like SyncReadMem()?



Read more here: https://stackoverflow.com/questions/66344890/syncreadmem-generated-verilog-vs-rocketchip-emitted-verilog

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