VHDL: is correct to use don’t care?

I am learning VHDL and for the university I've to write an encoder with priority with different describing styles like DataFlow, Behavioural, etc... The problem is when I have to describe it using statements like "case..when".

The base solution would be something like this:

architecture Behav_arch of encoderw_priority
begin

    case req is
        when "1000" | "1001" | "1010" | "1011" | "1100" | "1101" | "1110" | "1111" =>
            code <= "11";
        when "0100" | "0101" | "0110" | "0111" | "0100" | "0101" | "0110" | "0111" =>
            code <= "10";
        .....

    end case;           

end Behav_arch;

but I proposed this solution, that I think it's more readable:

entity encoderw_priority is
    port(
        req: in std_logic_vector(3 downto 0);
        code: out std_logic_vector(1 downto 0);
        active: out std_logic
    );
end encoderw_priority;

architecture Behav_Case of encoderw_priority is
begin

    process(req)
    begin

        case req is
            when "1---" =>
                code <= "11";
            when "01--" =>
                code <= "10";
            when "001-" =>
                code <= "01";
            when "0001" | "0000" =>
                code <= "00";
            when others =>
                code <= "XX";
         end case;
    
         case req is
            when "0000" =>
                active <= '0';
            when others =>
                active <= '1';
         end case;

    end process;

end Behav_Case;

Is this a correct solution? Simulating this, it works correctly. But I don't know if during synth or implementation it can bring some problems.

Thank you



Read more here: https://stackoverflow.com/questions/64287241/vhdl-is-correct-to-use-dont-care

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