I am getting this error when synthesizing my code, but I don't know what it means. It reads:
Error- net "Count or a directly connected net is driven by more than one source and not all drivers are three state.
It says the same errors for vectors count - count as well as for my
k values. The code is my representation of an SPI Master. The SPI master has an instantiation of a shift register that is used to push out information.
module SPIMaster(output reg SCLK, CS, MOSI, input EN, CLK, MISO, input [7:0] m_data); wire master_out; reg [4:0] count; wire [7:0] data_buff; wire SCLK1; reg master_in, c_sw, k, state, load; shiftReg register_out (master_out, data_buff, load, (~SCLK), master_in, m_data); assign SCLK1 = (~c_sw) | CLK; always@(posedge CLK) begin if(state) begin if (k == 1) begin state <= 0; c_sw <= 0; CS <= 1; count <= 0; k <= 0; load <= 0; end else begin state <= 1; c_sw <= 1; CS <= 0; end end else begin if (EN == 1) begin state <= 1; c_sw <= 1; CS <= 0; count <= 0; k <= 0; load <= 1; end else begin state <= 0; c_sw <= 0; CS <= 1; count <= 0; k <= 0; load <= 0; end end end always@(posedge SCLK1) begin if (CS == 0) master_in <= MISO; if (count == 7) begin load <= 0; end else if (count == 15)begin load <= 0; end else begin load <= 1; end end always@(negedge SCLK1) begin if (count == 23) k <= 1; else k <= 0; if (CS == 0) begin MOSI <= master_out; count <= count + 1; end end endmodule